Planar interconnecting network avoiding signal path crossovers



L. M. SPANDORFER T L PLANAR INTERCONNECTING NETWORK AVOIDING SIGNAL PATHCROSSOVERS Oct. 22, 1968 3,407,357

Filed Jan. 21, 1966 5 Sheets-Sheet 1 NAND 39 FIG. 3

C NAND Mb NAND b O b NAND lb 1- g i l A EXCLUSIVE I I OR 25 ss 27 i f fi FIG 2 EXCLUSIVE n EXCLUSIVE a 1 OR 5 OR 2s 55 l l INVENTORS l I LESTERM. SPANDORFER L. l ALBERT B. TONIK i SHIMON EVEN Oct. 22, 1968 u. M.SPANDORFER ETAL 3,407,357 PLANAR INTERCONNECTING NETWORK AVOIDING ISIGNAL PATH CROSSOVERS Filed Jan. 21, 1966 3 Sheets-Sheet 2 NAN: {NANDFJAND Oct. 22, 1968 PLANAR IINTERC Filed Jan. 21, 1966 SPANDORFER ET AONNECTING NETWORK AVOIDING SIGNAL PATH CROSSOVERS 3 Sheets-Sheet 3'INAQND c NAND NAND FIG. 5

NAND NAND NAND SUM 8w NAND C NAND -NAND CARRY FIG. 6 of NAND- NAND ANAND NAND NAND M B 51 NAND NAND NAND CARRY NAND FIG. 7

NAND NAND sum NAND NAND c Q NAND NAND- CARRY United States PatentABSTRACT OF THE DISCLOSURE The present device provides a logic networkconnected and located at each cross over the medium which connects theterminals of any other pair of associated terminals in the network.

This is a continuation-in-part of United States Patent of application,Ser. No. 346,570, filed Feb. 21, 1964, now

interconnecting signal arrangement for energy transmission systems, and,in particular, to planar connecting arrangements.

The present invention is an electrical system for simplicity but itshould be noted systems and the like.

When a number of electrical components, such as electrical circuit cardsin a computer, are joined together to form a system, these componentsmust be interconnected with one another.

The procedure for interconnecting these components has followed severaltechniques. In each of these techin servicing such computers, because ofthe random intermeshing of the wires, are manyfold.

The initial improvement on 3,407,357 Patented Oct. 22, 1968 there are nocrossovers.

Accordingly, it is an object of the present invention to provide animproved interconnecting network for an enfor an electrical system.

It is a further object of the present invention to provide aninterconnecting network for an energy transmitting system whichcrossovers of the media of terminals at an essential crossover point.

mina'ls of a second associated pair of terminals.

In accordance with the foregoing feature of the present embodiment ofthe invention taken in conjunction with the accompanying drawingswherein:

FIGURE 1 is a schematic diagram of an essential crossover of connectingmedia between four terminals.

FIGURE 2 is a schematic diagram of a logic device to be connectedbetween four terminals of an essential crossover.

FIGURE 3 is a schematic diagram of one embodiment of a device which canbe employed for the logic elements of FIGURE 2.

FIGURE 4 is a schematic diagram of a second embodiment of a device whichcan be employed for the logic elements of FIGURE 2.

FIGURE 5 is a schematic diagram of a conventional full adder employingthe minimum number of gates in accordance with a standard design.

FIGURE 6 is a schematic diagram of the full adder of FIGURE 5 with thewiring rearranged so that there is a reduction in the crossovers.

FIGURE 7 is a schematic diagram of the full adder with additional logicto eliminate the crossover shown in FIGURE 5 and FIGURE 6.

When an electrical system is inter-connected, i.e., when the variouselectrical components are wired together to form a system, theconnecting leads are positioned such that a number of essentialcrossovers result. An essential crossover should be understood to mean anecessary overlaying (or an apparent necessary overlaying) of a firstlead on a second lead in order that the first lead can connect twoelectrical terminals which lie along a first imaginary line which cuts asecond imaginary line lying between the two terminals that the secondlead connects. When the interconnection network of an electrical systemis first laid out, it may be that many leads cross over one another, butby re-routing the leads many of these crossovers can be eliminated,allowing only the essential crossovers to remain. Essential crossoversmay be only apparently necessary because the present invention providesfor their elimination.

The foregoing concept can be better understood by examining FIGURE 1which shows four terminals A-A and B-B. Assume that when the circuitcards (groups of electrical components) of a computer have been mountedon a single plane and wired together there remain four terminals orprinted circuit leads AA and B-B' unconnected. Assume that this signalsystem necessitates that A be connected to A and B be connected to B inorder to properly complete the interconnection of the circuit cards.Further assume that no other paths are possible. In other words, thecircuitry wired to the terminals A-A and B-B is such that if the lead 21were relocated to connect B-B by circumventing the terminal A this wouldresult in crossovers. For example, if the lead 21 were relocated to thesouth of terminal A, it would cross over the leads 11 and 13 which arealso connected to the terminal A, and in like manner if the lead 21 wererelocated to the north to circumvent terminal A, it would cross over thelines 15 and 17. From FIGURE 1, it can be seen that if the lead 19 wererelocated to circumvent B and B, it too would cut across other leads.Therefore, we must assume that in the system represented by FIGURE 1 theonly connection between B and B and A and A which can be made is aconnection as shown and would require a crossover which we have definedas an essential crossover.

As suggested earlier it should be noted here that although in theillustrative embodiment, the lines 19 and 21 have been identified aselectrical wires, these lines represent any form of energy transmissionmedia, such as ducts to transmit air in a pneumatic logic system.

Presently cross-overs are handled in a point-to-point wiring scheme onthe backboard by simply overlaying the connector media, the wires. Suchan arrangement does give rise to an occasional short circuit, and anoccasional spurious signal, but the more undesirable aspect of thisarrangement is the human error and difficulty in fabricating such anarrangement. The cross-over, per se, gives rise to no greater problems(other than those mentioned above) than the hand wiring scheme as awhole. The hand wiring schemes are space consuming; lead to human errorsin making such connections; are difiicult to service; and as theavailable space shrinks (as with airborne equipment) are almostimpossible to fabricate. Hence the interconnecting art has moved toprinted circuit multi-layer devices to take the place of theinterconncting wires.

In printed circuit multi-layer schemes the cross-over, per se, oftenbecomes a problem. There are serious problems in the reliability informing a conducting path through a substrate, or substrates, tocomplete connections from one terminal to another via a lower layer or alayer lying away from the layer adjacent the backboard. A great deal ofengineering and research effort is being spent to improve thisreliability. However, multi-layer printed circuit wiring, whatever itsadvantages over hand wiring, does not appear to be feasible as a meansfor interconnecting integrated circuits, especially when the integratedcircuits are formed as one integral mass. It would be ideal if integralcircuits, represented by wafers of semi-conductor material could beconnected together on the same plane to which they are mounted.

Consequently, the present invention deals with the problem of how toconnect the terminals B to B and A to A as viewed in FIGURE 1 withoutemploying the cross-over shown in FIGURE 1. As mentioned earlier it isto be understood that while the present invention is described inconnection with electrical circuits, other forms of energy transmissioncan take advantage of this invention. For instance, in a pneumaticsystem the present invention would have real utility in enabling astream of air to pass from A to A without having to tunnel a pair ofducts at the cross-over point.

Returning to the description of the electrical mode, the logic circuitto connect the four terminals A-A and B-B' will be described as beingmade up of three exclusive OR gates which in turn will be described asbeing made up of NAND gates. However, it should be understood that otherforms of logic can be used to accomplish the basic principle of a rightangular transmission of a signal, or signals, to accomplish an effectivetransmission of signals through a cross-over position. To be morespecific, the present invention while described in connection withexclusive OR gates and NAND gates should be considered as not limited tothese logical circuit arrangements.

Consider FIGURE 2 which shows a typical arrangement be included in thelogical device connecting the terminals A-A and B-B'. In the logicalblock 37 there are shown three exclusive OR gates 23, 25 and 27. It willbe recalled that the truth table for an exclusive OR gate is as follows.

In accordance with the foregoing truth table, if a signal a is appliedto the exclusive OR gate 23 and there is no signal b present, then thesignal a will appear on the lines 29, 31, 33 and 35. When the signal a,appears on lines 31 and 33 the exclusive OR gate 25 will not produce anoutput to the terminal B in accordance with the truth table. On theother hand when the signal a appears on line 35 and is transmitted tothe exclusive OR gate 27, which at the same time is not subject to thesignal b, there will be produced an output signal from the exclusive ORgate 27 to the terminal A. Accordingly an a signal can be transmittedfrom the terminal A to the terminal A.

In a symmetrical fashion it can be found that when the signal b istransmitted from the terminal B to the exclusive OR gates 23 and 27 itwill find its way through the network to the terminal B and will not betransmitted to the terminal A. Hence a signal b, in the absence of asignal a, can be transmitted from terminal B to terminal B. The lastcase we need consider is what happens when the signals a and b aretransmitted simultaneously. If the signals a and b are present, theexclusive OR gate 23 is inhibited and there is no output signal on thelines 29, 33 and 35. However, an a signal is transmitted on line 31 tothe exclusive OR gate 25, which has this a signal as the only inputthereto, and therefore this signal is transmitted to the terminal B. Ina similar manner, the signal b is transmitted to the exclusive OR gate27, which has only this one input signal thereto and therefore istransmitted to the terminal A. The above described right-angular signaltransmission effectively transmits a signal from B to B and from A to Asimultaneously because the signals, per se, have no identification otherthan a uniform pulse and the pulses applied and transmitted throughoutthe system are equal. Hence while the a signal actually activates theexclusive OR gate 25 to produce a b signal at B the circuitry receivingthe signal at B receives the signal as a b signal. In a like manner thecircuitry at terminal A receives the Signal thereat as an a signal,although it has been initiated by a b signal. It should be clearlyunderstood that the only time that a signal is transmitted to terminal Bas a result of an a signal initiation is when, in fact, a b signal hasbeen transmitted from the terminal B, and hence the effectivetransmission of the signal from B to B and from A to A is in order.

It becomes clear from the foregoing that the logic circuitry 37 can beconnected for every essential cross-over position and provide a planarconnection between any four terminals defining the essential cross-overposition in a system.

In order to carry the fabrication of the logic design one step furtherlet us consider what forms of circuitry might be employed to provide aplanar (that is, no crossover) exclusive OR gate. Consider the circuitryof FIG- URE 3. FIGURE 3 shows four NAND gates which are connected in apattern to provide an exclusive OR gate. The NAND gates can be thediode-transistor logic as disclosed in US. patent application No.524,062. The Boolean Algebra symbols are shown on the leads from theNAND gates which eventually provide an output from NAND gate 39 whenthere is an input of either a or b, but not in the presence or absenceof these input signals. The circuitry shown in FIGURE 3 is shown by wayof example only, and should not be considered as the only manner inwhich a planar exclusive OR gate can be designed. The use of the NANDgate in the circuitry of FIGURE 3 seems to be in order since theuniversality of the NAND gate is widely known, and widely used, in thefabrication of complete computer circuits.

In another form of logic a substitute for three exclusive OR gates ofFIGURE 2 can be developed with eight NAND gates or six NAND gates andtwo inverters as shown in FIGURE 4. The Boolean Algebra notations areshown in FIGURE 4 on the output lines of the logic devices, and can bereadily followed to show that a signal b can be transmitted to B from Bat the same time that signal a can be transmitted to A from A without acrossover.

Since the present invention makes it apparent that an essentialcross-over can be eliminated by substituting logic circuitry, it becomesobvious that essential cross-overs can be eliminated by redesigning theminimum logic of the logic network. That is to say, for any givenfunction, there is a minimum number of particular gates which arenecessary to accomplish the function under specified constraints. Thecharacteristics of the gates (which are considered as necessary andminimum) can be changed in order to reduce or eliminate cross-overs.Accordingly, then, an essential cross-over is to be further understoodto include any over laying of signal paths which would ordinarily resultwhile employing the minimum number of gates necessary to simplyaccomplish the function as might be dictated in accordance with anygeneral logic design technique, such as Boolean Algebra. To re-phrasethe foregoing, let it be understood that if a multi-terminal network isconnected in a planar mode (ie not in a multi-layer configuration)without cross-overs, but if that network would have had inherentcross-overs if the network had simply been designed to accomplish thefunction, (with a minimum number of gates), and such inherentcross-overs have been eliminated by changing the characteristics ordesign of the logic circuits normally involved then such a network isconsidered to be within the spirit of this invention. Such inherentcross-overs are considered to be within the definition of an essentialcross-over. Planar network is not to be considered limited to a flatplane.

It is the intent of this invention to provide a means by which logicchanges, whether they be the addition of more logic elements or thechange of logic elements per se, can be employed to overcomecross-overs.

Consider FIGURE 5. FIGURE 5 shows a conventional and minimum gate logicfor a full adder. It has been exhaustively proven that it is necessaryto have at least eight NAND gates to effect a full adder logicoperation. In FIGURE 5 there are shown eight NAND gates and if theproper pulses are applied the inputs A, B, and C, (C simply being shownas a double input), it will be found that: (1) for the presence of A, Band C we get both a sum and a carry; (2) for the presence of simply A, Bwe get zero sum and we get a carry; and (3) for the presence of any oneof A, B or C we get simply a sum.

FIGURE 6 shows the full adder with the wiring re arranged so that thereare only three cross-overs in particular at points 50, 51 and 52. Ifthere is a careful comparison made between the network of FIGURE 6 andthat of FIGURE 5 we find that we have reduced the number of cross-oversby twelve. Now the configuration of FIGURE 6 is as great a reduction aswe can attain in the number of cross-overs by the method of rewiring, orrerouting, the signal paths.

FIGURE 7 shows the full adder with no cross-overs. The cross-overs havebeen eliminated by substituting logic elements therefore in accordancewith the teaching of this invention. It can be noted in FIGURE 7 thatthere are eleven NAND gates or an increase of three NAND gates of theNAND gates of FIGURE 6. The three additional NAND gates are employed toeliminate the three cross-overs represented by the cross-overs 50, 51and 52 of FIGURE 6.

It should be readily apparent that the NAND gates shown in FIGURE 6 orFIGURE 5 per se might be internally changed, or expanded, so thatinstead of providing three separate NAND gates as shown in FIGURE 7, thelogic elements of FIGURES 5 or 6 simply take on other characteristics inaddition to being NAND gates which other characteristics enable theessential cross-overs to be eliminated.

According then to the present invention there can be employed at eachessential cross-over in an interconnection network a logic device whichwill effect a right angle energy signal transmission between adjacentterminals of a four-terminal essential cross-over position in order toeffect an energy signal transmission between the opposite terminals ofthe four-terminal array. Such an arrangement makes it possible to simplyand economically fabricate an entire interconnecting system on onesurface. The techniques of printed circuits are well known and thepresent invention lends itself to fabricating the entire interconnectingnetwork (without the logic devices) by printed circuits on one surfaceof a substrate. It follows that the requirement of providing backboardwiring or substituting multi-layered printed circuits therefor can :beeliminated. Circuit components and sub-assemblies can be connectedtogether via the same plane upon which they are mounted. Such anarrangement lends itself to great utility with respect to integratedcircuits wherein the sub-assemblies are fabricated as wafers ofsemiconductor material.

While the foregoing description sets forth a principle of the inventionin connection with specific apparatus, it is to be clearly understoodthat this description is made only by way of example and not as alimitation to the scope of the invention as set forth in the objectsthereof and in the accompanying claim.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

1. A network to accomplish a logic function for intelligent signalscomprising:

(a) a plurality of logic circuit means which represent the necessarylogic circuit means to be connected together to effect said function,said logic circuit means when connected together to effect said functionincluding at least first and second circuit paths which represent anessential crossover circuit;

(b) first, second, third and fourth circuit connections, said first andsecond circuit connections disposed to represent said first circuit pathand said third and fourth circuit connections disposed to represent saidsecond circuit path;

(c) further logic means connected to said first, second, third andfourth circuit connections and capable of transmitting intelligentsignals from said first circuit connection to said second circuitconnection in response to a condition of a signal at said first circuitconnection and no signal at said third circuit connection, and capableof transmitting an intelligent signal from said third circuit connectionto said fourth circuit connection in response to a circuit conditionwherein there is an intelligent signal present at said third circuitconnection and no intelligent signal present at said first circuitconnection and further capable of passing an intelligent signal fromsaid first circuit connection to said fourth circuit connection and fromsaid third circuit connection to said second circuit connection inresponse to intelligent signals being present in coincidence atrespectively said first and third circuit connections, said furtherlogic means being connected to said first, second, third and fourthcircuit connections along a single surface;

(d) circuitry means connecting said plurality of logic circuit meansalong a single surface.

References Cited Curtis, H. A.: The Design of Switching Circuits, VanNostrand, N.Y., 1962, pp. 324-325.

ARTHUR GAUSS, Primary Examiner.

J. D. FREW, Assistant Examiner.

